Yotta's technology had centered around the development of reference implementations for the new design layout data format OASIS (Open Artwork Systems Interchange Standard). In 2009 the company had extended the scope of its technology offerings to include design workflow cell view management using Smart Signatures. Both comprise the two major technological advances at the company.
Yotta had started as a company that delivered reference OASIS implementations to Foundries / Fabless / IDMs / EDA / Wafer and Mask Manufacturing Equipment / Mask Manufacturing companies. The world's first compliance OASIS regression test cases were delivered in September 2004. Yotta has served every major company within the semiconductor ecosystem plus many medium and small companies.
In late 2007, Yotta had been invited by a leading IDM to work on an effort to raise the clarity (pertinence) of the data they had in use throughout their globalized design workflows. They wanted a higher-level view of the data to be both constant and contextual at the same time. They wanted to have access to this dynamically referential higher level view to a granularity expressing the content of a layer within a leaf cell. Yotta developed a technology called Smart Signatures. It peers into the cell views (SPICE, Liberty, LEF, GDSII, Verilog, VHDL, DEF and OASIS) within this workflow, indexes and cross references what it finds. It, then, reports in real time what is changing where from PDK foundry release through 3rd Party IP/Fabless/IDM/System OEM library development, system level design, logic, layout integration to tapeout.
In 2010, Yotta introduced the first set of regression test cases for SEMI P44 OASIS.MASK. OASIS.MASK is a restricted subset of OASIS that enables the speedup and more efficient use of the new format OASIS targeting mask writers and inspection technology. The test cases are in use at major IDMs, Foundries, EDA and Mask equipment manufacturing companies.
In Mid 2012, Yotta released the first suite of stress test cases that simulate the layout of commercial device designs at the 20 and 14 nm nodes. The company is about to release stress test cases from both 10 and 7 nm. They exercise design and other computationally intensive hardware and software throughout the semiconductor workflow. Yotta's current customers include leading EDA and mask manufacturing equipment companies.
In December 2013, Yotta began a move to bring a view of the semiconductor industry workflow to the cloud using smart signatures. The company's goal is to have its first customers by September 2015.
As more of the of the integrated circuit design workflow has become virtualized as an abstracted view of what is possible in manufacturing, less of a perspective about how the two are tied together is visible to the designer. As the sophistication of integrated circuit designs have increased, the sophistication of the virtualized representations of those circuits, as they relate to manufacturing, have increased. The fit of information within this flow has had to be more concise / matters related to compliance honed so that tools interpret data similarly / matters related to tool-to-tool, interface-to-interface, interchange-to-interchange layout equivalence refined. As the size of the designs have increased to tens to hundreds of GBs of OASIS and GDSII data, today's computational abilities have had to increase dramatically.
As they've attempted to have all of this converge into a workable solution, the output from the tools within this workflow have not synced / the view not as clear as they'd like. Yotta's technology facilitates this convergence. Its focus being compliance / pertinence / equivalence / performance.
* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan 4768896, Korea 10-1580258