OASIS® is a Registered Trademark of Thomas Grebinski
SIMULATED 14 nm SRAM STRESS TEST CASE
This 14 nm design simulates a merchant single-port Static Random Access Memory (SRAM). It is 9299.7 microns wide and 14705.5 microns high, and features:

  • 14 nm gate length, 28 nm metal pitch;
  • 6-transistor core cell using the Ishida category 4 layout style with unidirectional gate layout;
  • realistic-looking decoder, equalizer, and sense amplifier circuits around the periphery;
  • relatively small 64 kilobit page size to maximize the number of layers of hierarchy;
  • spare SRAM pages;
  • three layers of metal;
  • 2 gigabits (256 megabytes) of usable memory plus ECC in each word;
  • 16,257,122,304 transistors in SRAM core cells;
  • 17,337,638,556 transistors total including peripheral and top-level control logic; and
  • polygons colored for double patterning on gate, contact, and metal layers.

This test case includes multiple OASIS files, generated using different repetition analysis strategies:

  • Type 10 and 11 (random) repetitions only;
  • type 4-7 (1-D irregular vector) and 10-11 repetitions;
  • all orthogonal repetition types (1-7, 10-11) with medium analysis effort;
  • all orthogonal repetition types (1-7, 10-11) with high analysis effort.

The preliminary version of the GDSII file is about 260 megabytes in size and each copy of the OASIS file is about 14 megabytes in size.

Use this design to ensure your repeated-object code is ready for tomorrow's designs. Nearly all of the design is SRAM core cells.
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"The Company's technology established a common expectation amongst suppliers and customers regarding matters of OASIS compliance, performance and interoperability" 

Naoya Hayashi
Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
typedef struct _oasisReaderPath {
       oasisUInt layer,dataType,halfWidth;
       oasisInt startExt,endExt;
       rawPointList *ptList;
       oasisPropertyList *propList;
} oasisReaderPath;
Production 14 nm Planar 1 Gb Merchant SRAM Test Case Data Sheet
Sample 20 ands 14 nm Planar Layout Stress Test Cases
OAS = OASIS
GDS = GDSII
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© 2008-2018 Yotta Data Sciences, Inc. All rights reserved.
* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan  4768896, Korea 10-1580258
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