BLOCKAGE MASK + DIFFRACTION GRATING + FIN PITCH DOUBLING VARIANT
A preliminary version of a 7 nm finFET eight-core commercial CPU synthetic design/stress test case is available for download now on the Yotta FTP site. This is intended to be similar to a high-end Intel or AMD processor chip.
14 nm drawn gate length
40 nm SRAM contacted gate pitch
80 nm by 360 nm single-port SRAM core bit cell size
80 nm by 540 nm two-port SRAM core bit cell size
120 nm by 648 nm three-port SRAM core bit cell size
two layers of local interconnect
six layers of metal
18 nm fin pitch
self-aligned double patterning (SADP) for fins
1-D gate layer
diffraction gratings for poly, local interconnect, and metal
blockage masks to pattern diffraction gratings
Each processor core has 3-port SRAM for the level 1 cache and register blocks, plus 2-port SRAM for the level 2 cache. Additionally, there is 1-port level 3 cache SRAM around the perimeter of the die. The overall design is about 7,600.5 microns wide and 6,881.1 microns high.
The family of 7 nm finFET design rules used for this design has self-aligned double pattern (SADP) fin generation, a 14 nm drawn gate length, a 40 nm contacted gate pitch, two layers of local interconnect, six metal layers, 40 nm routing pitches for lower metal layers, and 48 nm routing pitches for upper metal layers (metal 4 and up).
All geometry on the transistor gate, first local interconnect, metal 2, and metal 4 layers is vertical. All geometry on the second local interconnect, metal 3, and metal 5 layers is horizontal. Diffraction gratings with blockage masks are drawn for gate, local interconnect, and metal layers.
Design rule variants in this family can have 2-D routing on any subset of gate or routing layers, diffraction gratings with blockage or cut masks on any subset of gate or routing layers, or different color counts. Contact Yotta Data Sciences for more information or to request a demonstration file using a particular variant.