Yotta's Library Release Reporter occurs after a new library has been approved for release to Fabless and System OEM design project teams / after Yotta's release Auditor has been invoked and all problems fixed and all cell views referential with their corresponding views.
At this point, the Library team makes the new release available. Typically, included with this release is a list of which cells had changed and a general description of the rationale for the changes. What, specifically, had changed, where and how is not included. The technological capacity to do so is not available today. Having Yotta's IP Library release Auditing technology invoked allows for such a greater disclosure. To have such a disclosure useful, the design teams will want to know whether the cell views they have in use are supposed to be in use. Again, the technological capacity to do so is not available today.
Yotta's Release Reporter comes with a Point Tool that a design team can use to (1) make certain what they have in use is approved and (2) that all cell views they have in use are corresponding versions of the cell views in the new release that had changed. With this Auditor, a design team will be able to compare the new release with its block or chip-level design. They'll be able to determine the differences and, subsequently, the meaning of the changes in the new library release to them.
First, the design team will verify that its deign is current / that the cell views it has in use, for example, are approved, have not been deprecated or had missed a critical update. Once having cleared this audit, the same Auditor can be used to run a comparison against the new release.
The result will be an unprecedented reporting of what had changed from the current expression of a team's design to the latest release. Nothing will be missed. Non-relevant data having nothing to with the functional characteristics of the design will be reported separately. As shown above, the rest will be meaningful to the team.
With this detail at their fingertips, design teams will be able to make more informed decisions about the impact the new release might have on their designs. If any, how much of a rework will be necessary? Is it just one cell within one instance of a cell block that has change? Or, many instances of the same cell view embedded in different blocks of IP? Will an in-Place optimization suffice? With Yotta's Release reporter, design teams will be able to design more aggressively at less cost and risk to design success.
INTELLECTUAL PROPERTY (IP) AND LIBRARY RELEASE REPORTER*
OASIS® is a Registered Trademark of Thomas Grebinski
View (OASIS), File 1035, Cell x
Cell Body Layer non-geometry
v.1, v.2, v.n
Indexed File Content by Cell
Cell View Dependencies
. . . SPICE models, Design Rules, Circuit Extraction Parameters
. . . SPICE, Liberty, LEF, GDSII, OASIS
Logic Design / Synthesis
. . . Verilog, VHDL, Liberty
. . . Verilog, VHDL, DEF
. . . Liberty, LEF, GDSII, OASIS, DEF
. . . GDSII, OASIS
"... The Company's technology plays a substantial role helping us isolate and fix problems before they become silicon issues ..."
Smart Signature Generation
PLM / Configuration / Data Managment
PDK / Cell / Block / Chip
Master Signature Database
Workflow Auditor Point Tools
© 2008-2018 Yotta Data Sciences, Inc. All rights reserved.
* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan 4768896, Korea 10-1580258
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