OASIS® is a Registered Trademark of Thomas Grebinski
10 nm finFET MERCHANT 1 Gb SRAM STRESS TEST CASE
FIN PITCH DOUBLING VARIANT
A preliminary version of a 10 nm finFET gigabit (128 megabytes) SRAM synthetic design/stress test case is available for download now on the Yotta FTP site. It features:
16 nm drawn gate length
48 nm SRAM contacted gate pitch
96 nm by 400 nm single-port SRAM core bit cell size
two layers of local interconnect
three layers of metal
20 nm fin pitch
self-aligned double patterning (SADP) for fins
1-D gate layer
Fin Pitch Doubling
This design simulates a commercial 128 megabyte single-port SRAM using 10 nm finFET design rules. It is 8,942.6 microns wide and 9,166.5 microns high with a total of 8,561,079,118 transistors.
The family of 10 nm finFET design rules used for this design has self-aligned double pattern (SADP) fin generation, a 16 nm drawn gate length, a 48 nm contacted gate pitch, two layers of local interconnect, six metal layers, 48 nm routing pitches for lower metal layers, and 60 nm routing pitches for upper metal layers (metal 4 and up). This design uses only three metal layers, as is typical for merchant SRAMs.
All geometry on the transistor gate is vertical. No diffraction gratings are drawn.
Design rule variants in this family can have 2-D routing on any subset of gate or routing layers (except metal 1), or diffraction gratings with blockage or cut masks on any subset of gate or routing layers. Contact Yotta Data Sciences for more information or to request a demonstration file using a particular variant.