Yotta's Intellectual Property (IP) Ownership Auditor is similar to the technology that we're offering as our Hard IP Royalty Auditor and Identity Manager. The use-model, though, is different / the reporting is different. There are situations where a company questions whether its IP is in use by others who've not a license. Or, there have been situations where a company suspects that its IP part of a device in manufacturing at a Foundry. Unless the IP is an exact copy, the determination can be costly and the outcome; especially when the suspected IP has been obfuscated in some way that apparently masks its identity, uncertain.
Yotta's Ownership Auditor creates a snapshot of all of the cell views from their source through cell, block and chip level design. It stores a versioned history of the cell views that had been used to create the IP. This signature database can be compared against the signatures created for the suspected IP. A complete mapping of matches will be reported including partial matches where there have been attempts to obfuscate the use of the IP.
The Master Database and Ownership Auditor Point Tool can be stored and invoked from a laptop. The owner's IP remains with the owner. The audit is secure for both parties. Only the signatures are stored compared for matching cell views. The technology can be used, by concerned parties in litigation, mediation or informal audits. Rather than a manual audit taking days, weeks or even months, Yotta's technology reports matches within billions of cell views in multiple data formats in a matter of minutes.
INTELLECTUAL PROPERTY (IP) OWNERSHIP AUDITOR*
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Tapeout
In-place Optimization
Layout Integration
Block-level Design
Floorpanning
Logic Design/Synthesis
System-level Design
Library Release Reporter
Library Development
Foundry
Fabless
IDM
System OEM
3rd Party IP
Manufacturing
Process Development
PDK Release
IP View x
File-level non-layer
File-level layer
File-level non-functional
Cell x
Cell Interface non-layer
Cell Interface layer
Cell non-functional
Cell Body
Cell Body layer
Cell Body layer geometry
Cell Body Layer non-geometry
SS n
SS I
SS II
SS III
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Company A
Indexed File Content by Cell
SS o
SS i
SS ii
SS iii
Company B
PDK
SPICE
Liberty
LEF
GDSII
OASIS
Verilog
VHDL
DEF
Cell View Dependencies
PDK
. . . SPICE models, Design Rules, Circuit Extraction Parameters
Library Development
. . . SPICE, Liberty, LEF, GDSII, OASIS
Logic Design / Synthesis
. . . Verilog, VHDL, Liberty
Floor Planning
. . . Verilog, VHDL, DEF
Layout Integration
. . . Liberty, LEF, GDSII, OASIS, DEF
Tapeout
. . . GDSII, OASIS
"... The Company's technology plays a substantial role helping us isolate and fix problems before they become silicon issues ..."
Lisa Fisher
Engineering Manager
Texas Instruments
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Smart Signature Generation
API
PLM / Configuration / Data Managment
PDK / Cell / Block / Chip
Master Signature Database
Smart Signatures
OAS = OASIS
GDS = GDSII
Workflow Auditor Point Tools
TM
®
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NEW at Yotta Data Sciences
* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan 4768896, Korea 10-1580258, Israel 209907, European Patent 2310967.
OASIS® is a Registered Trademark of Thomas Grebinski
© 2008-2024 Yotta Data Sciences, Inc. All rights reserved.
February 16, 2024- Yotta is offering, to qualified partners, a six-month evaluation-period, with support, for its SEMI P39-0416 OASIS Reader/Writer Source Code.
Visit Page: OAS Reader/Writer
Visit Page: OAS Source Code
