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7 nm 8-CORE finFET MERCHANT CPU STRESS TEST CASE
 CUT MASK + DIFFRACTION GRATING + FIN PITCH DOUBLING VARIANT
A preliminary version of a 7 nm finFET eight-core commercial CPU synthetic design/stress test case is available for download now on the Yotta FTP site. This is intended to be similar to a high-end Intel or AMD processor chip.​

  • 14 nm drawn gate length
  • 40 nm SRAM contacted gate pitch
  • 80 nm by 360 nm single-port SRAM core bit cell size
  • 80 nm by 540 nm two-port SRAM core bit cell size
  • 120 nm by 648 nm three-port SRAM core bit cell size
  • two layers of local interconnect
  • five layers of metal
  • 18 nm fin pitch
  • self-aligned double patterning (SADP) for fins
  • 1-D gate layer
  • 1-D routing
  • diffraction gratings for poly, local interconnect, and metal
  • cut masks to pattern diffraction gratings

​Each processor core has 3-port SRAM for the level 1 cache and register blocks, plus 2-port SRAM for the level 2 cache. Additionally, there is 1-port level 3 cache SRAM around the perimeter of the die. The overall design is about 7,600.5 microns wide and 6,881.1 microns high.

​The family of 7 nm finFET design rules used for this design has self-aligned double pattern (SADP) fin generation, a 14 nm drawn gate length, a 40 nm contacted gate pitch, two layers of local interconnect, six metal layers, 40 nm routing pitches for lower metal layers, and 48 nm routing pitches for upper metal layers (metal 4 and up).

All geometry on the transistor gate, first local interconnect, metal 2, and metal 4 layers is vertical. All geometry on the second local interconnect, metal 3, and metal 5 layers is horizontal. Diffraction gratings with blockage masks are drawn for gate and local interconnect layers; diffraction gratings with cut masks are drawn for the metal 2 through metal 5 layers.

Design rule variants in this family can have 2-D routing on any subset of gate or routing layers, diffraction gratings with blockage or cut masks on any subset of gate or routing layers, or different color counts. Contact Yotta Data Sciences for more information or to request a demonstration file using a particular variant.
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Production 7 nm finFET 8-Core (1011) Merchant CPU Test Case Data Sheet
"The Company's technology established a common expectation amongst suppliers and customers regarding matters of OASIS compliance, performance and interoperability" 

Naoya Hayashi
Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
typedef struct _oasisReaderPath {
       oasisUInt layer,dataType,halfWidth;
       oasisInt startExt,endExt;
       rawPointList *ptList;
       oasisPropertyList *propList;
} oasisReaderPath;
Sample finFET Design Test Cases
OAS = OASIS
GDS = GDSII
Workflow Auditor Point Tools
{0|1} = Cut Mask
{0|1} = Blockage Mask
{0|1} = Diffraction Grating
{0|1} = Fin Pitch Doubling
0 = Not a variant
1 = Variant
| = or
© 2008-2018 Yotta Data Sciences, Inc. All rights reserved.
* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan  4768896, Korea 10-1580258
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