SIMULATED 20 nm MERCHANT CPU STRESS TEST CASE
This 20 nm design simulates a merchant microprocessor chip, e.g. an Intel or AMD 8-core design. It is 11227.1 microns wide and 11223.7 microns high. It features:
- 20 nm gate length, 64 nm SRAM metal pitch, 72 nm logic routing pitch;
- eight large, identical processor cores;
- 64 KB of level 1 cache SRAM per processor core;
- 256 KB of level 2 cache SRAM per processor core;
- 39 MB of shared level 3 cache SRAM;
- complex multi-level hierarchial processor floorplan;
- a wide range of block sizes and shapes;
- five layers of metal in logic areas; and
- polygons colored for double patterning on gate, contact, and metal layers.
After hierarchy expansion, the design has about 750 million transistors in the processor core logic and almost 2 billion transistors in cache SRAM, for a total of about 2.7 billion transistors.
The preliminary version of the GDSII file is about 17 gigabytes; the OASIS file is about 0.93 gigabytes.
With large blocks repeated at high levels of the design hierarchy, this test case will exercise your hierarchy management code in entirely different ways than one of the merchant SRAM test cases.
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"The Company's technology established a common expectation amongst suppliers and customers regarding matters of OASIS compliance, performance and interoperability"
Naoya Hayashi
Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
typedef struct _oasisReaderPath {
oasisUInt layer,dataType,halfWidth;
oasisInt startExt,endExt;
rawPointList *ptList;
oasisPropertyList *propList;
} oasisReaderPath;
Production 20 nm Planar CPU Stress Test Case Data Sheet
Sample 20 ands 14 nm Planar Layout Stress Test Cases
OAS = OASIS
GDS = GDSII
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* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan 4768896, Korea 10-1580258, Israel 209907, European Patent 2310967.
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