small processor core and 128 KB of program SRAM per processing unit;
simulated serializer/deserializer (SerDes) with 64 KB of SRAM per processing unit;
8 MB of routing table SRAM in the center of the die;
five layers of metal in logic areas; and
polygons colored for double patterning on gate, contact, and metal layers.
After hierarchy expansion, the design has about 2.51 billion transistors, with 374 million bits of SRAM (including ECC) and about 23.5 million placed standard cell instances.
The preliminary version of the GDSII file is about 6.0 gigabytes; the OASIS file is about 347 megabytes.
This design provides a wide mix of design styles (SRAM, processors, and random logic) with some high-level repetition and a medium-size random logic block (about 2.1 million placed instances). The simulated SerDes blocks will eventually have representative analog circuits.