20 nm NETWORK PROCESSOR STRESS TEST CASE
This 20 nm design simulates a network processor chip. It is 8234.5 microns wide and 8010.2 microns high. It features:
- 20 nm gate length, 64 nm SRAM metal pitch, 72 nm logic routing pitch;
- 24 identical network processing units (NPUs);
- 1 MB of packet storage SRAM per processing unit;
- small processor core and 128 KB of program SRAM per processing unit;
- simulated serializer/deserializer (SerDes) with 64 KB of SRAM per processing unit;
- 8 MB of routing table SRAM in the center of the die;
- five layers of metal in logic areas; and
- polygons colored for double patterning on gate, contact, and metal layers.
After hierarchy expansion, the design has about 2.51 billion transistors, with 374 million bits of SRAM (including ECC) and about 23.5 million placed standard cell instances.
The preliminary version of the GDSII file is about 6.0 gigabytes; the OASIS file is about 347 megabytes.
This design provides a wide mix of design styles (SRAM, processors, and random logic) with some high-level repetition and a medium-size random logic block (about 2.1 million placed instances). The simulated SerDes blocks will eventually have representative analog circuits.
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"The Company's technology established a common expectation amongst suppliers and customers regarding matters of OASIS compliance, performance and interoperability"
Naoya Hayashi
Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
typedef struct _oasisReaderPath {
oasisUInt layer,dataType,halfWidth;
oasisInt startExt,endExt;
rawPointList *ptList;
oasisPropertyList *propList;
} oasisReaderPath;
Production 20 nm Planar SoC Network Processor Stress Test Case Data Sheet
Sample 20 ands 14 nm Planar Layout Stress Test Cases
OAS = OASIS
GDS = GDSII
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* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan 4768896, Korea 10-1580258, Israel 209907, European Patent 2310967.
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