A preliminary version of a 7 nm finFET eight-core commercial CPU synthetic design/stress test case is available for download now on the Yotta FTP site. This is intended to be similar to a high-end Intel or AMD processor chip.
16 nm drawn gate length
48 nm SRAM contacted gate pitch
96 nm by 400 nm single-port SRAM core bit cell size
96 nm by 600 nm two-port SRAM core bit cell size
144 nm by 760 nm three-port SRAM core bit cell size
two layers of local interconnect
six layers of metal
20 nm fin pitch
self-aligned double patterning (SADP) for fins
1-D gate layer
Each processor core has 3-port SRAM for the level 1 cache and register blocks, plus 2-port SRAM for the level 2 cache. Additionally, there is 1-port level 3 cache SRAM around the perimeter of the die. The overall design is about 9,012.5 microns wide and 8,163.8 microns high.
The family of 10 nm finFET design rules used for this design has self-aligned double pattern (SADP) fin generation, a 16 nm drawn gate length, a 48 nm contacted gate pitch, one layer of local interconnect, six metal layers, 48 nm routing pitches for lower metal layers, and 60 nm routing pitches for upper metal layers (metal 4 and up).
All transistor gate layer geometry is vertical. Because the metal 2 through metal 5 layers allow 2-D routing, they have via doubling. Except for this, geometry on any given metal layer runs in a single direction (horizontal or vertical).
Design rule variants in this family can have 1-D routing on any subset of gate or routing layers (except metal 1), or diffraction gratings with blockage or cut masks on any subset of gate or routing layers. Contact Yotta Data Sciences for more information or to request a demonstration file using a particular variant.