7 nm finFET MERCHANT 1 Gb SRAM STRESS TEST CASE
BLOCKAGE MASK + DIFFRACTION GRATING + FIN PITCH DOUBLING VARIANT
A preliminary version of a 7 nm finFET gigabit (128 megabytes) SRAM synthetic design/stress test case is available for download now on the Yotta FTP site. It features:
- 14 nm drawn gate length
- 40 nm SRAM contacted gate pitch
- 80 nm by 360 nm single-port SRAM core bit cell size
- two layers of local interconnect
- three layers of metal
- 18 nm fin pitch
- self-aligned double patterning (SADP) for fins
- 1-D gate layer
- 1-D routing
- diffraction gratings for poly, local interconnect, and metal
- blockage masks to pattern diffraction gratings
This design simulates a commercial 128 megabyte single-port SRAM using 7 nm finFET design rules. It is 7,447.0 microns wide and 8,083.4 microns high with a total of 8,616,691,110 transistors.
The family of 7 nm finFET design rules used for this design has self-aligned double pattern (SADP) fin generation, a 14 nm drawn gate length, a 40 nm contacted gate pitch, two layers of local interconnect, six metal layers, 40 nm routing pitches for lower metal layers, and 48 nm routing pitches for upper metal layers (metal 4 and up). This design uses only three metal layers, as is typical for merchant SRAMs.
All geometry on the transistor gate, first local interconnect, and metal 2 layers is vertical. All geometry on the second local interconnect and metal 3 layers is horizontal. Diffraction gratings with blockage masks are drawn for gate, local interconnect, and metal layers. Most critical design layers have three colors; metal 1 has four colors because it has 2-D routing.
Design rule variants in this family can have 2-D routing on any subset of gate or routing layers, diffraction gratings with blockage or cut masks on any subset of gate or routing layers, or different color counts. Contact Yotta Data Sciences for more information or to request a demonstration file using a particular variant.
Production 7 nm finFET 1 Gb (0111) Merchant SRAM Test Case Data Sheet
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"The Company's technology established a common expectation amongst suppliers and customers regarding matters of OASIS compliance, performance and interoperability"
Naoya Hayashi
Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
typedef struct _oasisReaderPath {
oasisUInt layer,dataType,halfWidth;
oasisInt startExt,endExt;
rawPointList *ptList;
oasisPropertyList *propList;
} oasisReaderPath;
Sample finFET Design Test Cases
OAS = OASIS
GDS = GDSII
Workflow Auditor Point Tools
{0|1} = Cut Mask
{0|1} = Blockage Mask
{0|1} = Diffraction Grating
{0|1} = Fin Pitch Doubling
0 = Not a variant
1 = Variant
| = or
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* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan 4768896, Korea 10-1580258, Israel 209907, European Patent 2310967.
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