Yotta's smart-XOR verifies the layout equivalence between two written OASIS and/or GDSII files. The verification can be between tools and versions of tools that write out GDSII and OASIS data. The technology uses Yotta's Smart Signature technology.
Yotta's smart-XOR is more than 100X faster than today's XORs. It reports meaningful layout differences between cell views, both geometric and non-geometric differences.
It is smart. It has the ability to create canonical expressions of the layout of a cell, block or chip-level design, whether GDSII or OASIS, without flattening the data. The design hierarchy is maintained. As shown above, the layout equivalence report is to the leaf cell layer level.
Yotta's smart-XOR can be a reference implementation for layout equivalence within a design workflow from standard cell library development through block and chip level layout integration and tapeout. It can be used to check for layout equivalence at the foundry level as well in mask and wafer manufacturing.
Yotta's technology can qualify the XORs used in EDA tools or be integrated into EDA and mask and wafer manufacturing software packages.