14 nm finFET MERCHANT 1 Gb SRAM STRESS TEST CASE
NO VARIANTS
A preliminary version of a 14 nm finFET gigabit (128 megabytes) SRAM synthetic design/stress test case is available for download now on the Yotta FTP site. It features:
- 18 nm drawn gate length
- 65 nm SRAM contacted gate pitch
- 130 nm by 600 nm single-port SRAM core bit cell size
- two layers of local interconnect
- three layers of metal
- 40 nm fin pitch
- 2-D gate layer
- 2-D routing
This design simulates a commercial 128 megabyte single-port SRAM using 10 nm finFET design rules. It is 12,046.3 microns wide and 13,413.4 microns high with a total of 8,569,132,296 transistors transistors.
The family of 14 nm finFET design rules used for this design has an 18 nm drawn gate length, a 64 nm theoretical contacted gate pitch, one layer of local interconnect, six metal layers, 64 nm routing pitches for lower metal layers, and 84 nm routing pitches for upper metal layers (metal 4 and up).
All transistor gates are vertical; only gate layer routing within standard cells or SRAM circuits can be horizontal.
Because the metal 2 and metal 3 layers allow 2-D routing, they have via doubling. Except for this, geometry on any given metal layer runs in a single direction (horizontal or vertical).
Design rule variants in this family can have 2-D routing on any subset of gate or routing layers (except metal 1), or diffraction gratings with blockage or cut masks on any subset of gate or routing layers. Contact Yotta Data Sciences for more information or to request a demonstration file using a particular variant.
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typedef struct _oasisReaderPath {
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} oasisReaderPath;
Production 14 nm finFET 1 Gb (0000) Merchant SRAM Test Case Data Sheet
Sample finFET Design Test Cases
OAS = OASIS
GDS = GDSII
Workflow Auditor Point Tools
{0|1} = Cut Mask
{0|1} = Blockage Mask
{0|1} = Diffraction Grating
{0|1} = Fin Pitch Doubling
0 = Not a variant
1 = Variant
| = or
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