OASIS® is a Registered Trademark of Thomas Grebinski
SIMULATED 20 nm MERCHANT SRAM STRESS TEST CASE
This 20 nm design simulates a merchant single-port Static Random Access Memory (SRAM). It is 15639.6 microns wide and 10976.8 microns high, and features:

  • 20 nm gate length, 64 nm metal pitch in core cell;
  • 6-transistor core cell using the Ishida category 4 layout style with unidirectional gate layout;
  • realistic-looking decoder, equalizer, and sense amplifier circuits around the periphery;
  • 32 kilobit page size;
  • three layers of metal;
  • 1 gigabit (128 megabytes) of usable memory plus ECC in each word;
  • 7,650,410,496 transistors in SRAM core cells;
  • 7,882,866,024 transistors total including peripheral and top-level control logic; and
  • polygons colored for double patterning on gate, contact, and metal layers.

This is a high-repetition design, so the GDSII file is about 103 megabytes and the OASIS file is about 5 megabytes.

Use this design to ensure your repeated-object code is ready for tomorrow's designs. Nearly all of the design is SRAM core cells.

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"The Company's technology established a common expectation amongst suppliers and customers regarding matters of OASIS compliance, performance and interoperability" 

Naoya Hayashi
Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
typedef struct _oasisReaderPath {
       oasisUInt layer,dataType,halfWidth;
       oasisInt startExt,endExt;
       rawPointList *ptList;
       oasisPropertyList *propList;
} oasisReaderPath;
Sample 20 ands 14 nm Planar Layout Stress Test Cases
Production 20 nm Planar 1 Gb Merchant SRAM Test Case Data Sheet
OAS = OASIS
GDS = GDSII
Workflow Auditor Point Tools
© 2008-2018 Yotta Data Sciences, Inc. All rights reserved.
* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan  4768896, Korea 10-1580258
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