SAMPLE 14 nm, 10 nm and 7 nm finFET STRESS TEST CASES
Preliminary versions of a set of finFET demonstration synthetic design/stress test cases are now available. Each is a small processor core, similar to an ARM processor, that demonstrates the cell generation, placement and routing, and floorplanning capabilities of the Yotta Data Sciences synthetic design/stress test generator. The processor cores include 1-port cache SRAM and small 2-port register blocks. Their sizes range from about 517.1 microns wide and 469.1 microns high (14 nm) to 320.2 microns wide and 278.5 microns high (7 nm).

Variants are available for families of 14 nm, 10 nm, and 7 nm finFET technologies. These demonstrate: self-aligned double patterning (SADP) for fins; 1-D or 2-D gate and routing layers; diffraction gratings for gate and routing layers; and cut or blockage masks to pattern the diffraction gratings. All transistor gates are vertical; only gate layer interconnect can be horizontal. 2-D routing layers have via doubling.

Contact Yotta Data Sciences for more information, to request a demonstration file using a particular variant within a family, or to request a custom design with different design rules.


Sample finFET Layout Stress Test Case Download Request
Sample finFET Layout Stress Test Case Data Sheet Request
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Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
typedef struct _oasisReaderPath {
       oasisUInt layer,dataType,halfWidth;
       oasisInt startExt,endExt;
       rawPointList *ptList;
       oasisPropertyList *propList;
} oasisReaderPath;
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{0|1} = Cut Mask
{0|1} = Blockage Mask
{0|1} = Diffraction Grating
{0|1} = Fin Pitch Doubling
0 = Not a variant
1 = Variant
| = or
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