"The Company's technology established a common expectation amongst suppliers and customers regarding matters of OASIS compliance, performance and interoperability"
Electronic Device Laboratory
Dai Nippon Printing Co., Ltd
OASIS® is a Registered Trademark of Thomas Grebinski
Factory to Design to Factory Workflow Integrity and Effectiveness
Yotta's Product offerings have focused on the clarity and the effectiveness of the developing design information within the factory to 3rdParty IP/IDM/Fabless/System OEM workflow.
Yotta has placed its emphasis on the development of software solutions that manage the quality, expression and the useful life of a company's strongest asset; the data (the Intellectual Property) that represents an abstracted view of, what is supposed to be, a manufacturable integrated circuit. We develop and sell software that serves the following domains and disciplines with the semiconductor factory to design workflow:
. . . Domains
. Foundry, Fabless, IDM, System OEM, EDA, Capital Equipment, 3rd Party IP and Merchant Mask
. . . Disciplines
. Data format compliance for SEMI P39 OASIS and P44 OASIS.MASK
. OASIS reference implementations (source code and utilities)
. Design and manufacturing tool stress test cases
. Factory to design workflow data integrity auditors
OASIS is a data format that both represents and expresses an abstracted physical view of an integrated circuit as it should be manufactured. Its abstracted view is born out of an iterative process that attempts to bring the accuracy of this abstracted view as close as possible to what can be done in manufacturing. In other words, the format represents data that is as close of an abstraction to manufacturing as possible. Therefore, nearly every domain makes use of the format. Yotta's addressable market is this domain. It serves the top 10 of each including the rest of the medium to smaller sized companies who offer products at the leading edge of semiconductor technology.
An OASIS implementation code base can be as much as 30X the size of the code base for GDSII. Its implementation is far more sophisticated in its expression meeting similar jumps in the sophistication and size of the designs it expresses. The year 2000 saw GDSII designs at 50GBs. At 14nm, they can be 300GBs. Equivalent OASIS representations can be as small as 1 and 6GBs; 50X smaller. Yotta offers regression test cases for both OASIS and OASIS.MASK. OASIS.MASK is a restricted subset of OASIS tailored for mask writer and inspection systems. Yotta was the first to offer regressions to its domain customers.
Yotta developed the first commercial reference implementation for the new format OASIS. It included source code that allowed the building of reference level readers, writers and utilities. They helped some of Yotta's customers develop their own internal capability and helped others by being able to start with a world class implementation able to fit within a multi-billion dollar semiconductor workflow.
Stress Test Cases
One of the largest impediments to the development of tools able to handle more sophisticated and larger designs computationally. Realistic commercial level designs through which to exercise such tools have never been available, in part, because design teams do not have them yet and because they are considered proprietary. Yotta developed a stress test case generator that can simulate next generation commercial designs. They're not functional but close to being so. They're used by EDA and semiconductor capital equipment companies who are working at design nodes 20, 14, 10 and 7 nm.
Workflow Data Integrity Auditors
The factory to design to factory workflow is heavily siloed. Before and after the interfaces and interchanges are different data formats. Between each are numerous types of design tools and design styles having their own, sometimes proprietary, data formats. Yotta found a way to peer into this data and tie it together into one dynamically referential view of a granularity to a layer in a leaf cell, of a comprehensiveness that spans all levels of the workflows design hierarchy from cell to chip-level design. It offers both point tools and is working with customers to develop a higher level ecosystem view of the industry's workflow that is both constant and contextual at the same time.
OASIS Source Code
20, 14, 10 and 7 nm
Planar, FD-SOI, FinFET
Point, Cloud SaaS
Hard IP Royalty
Yotta's objective has been to offer products that fixes the nearsightedness of the semiconductor technology workflow. Yotta believes that the needed information to advance semiconductor technology is there but blurred (out of focus) / its finest details not resolvable. Having access to compliance technology reduces the number of different interpretations of how design data should be represented and expressed. Reference implementations help solve workflow tool interface and interchange conflicts quickly. Stress test cases prepare design and manufacturing tools for next generation operations that will inevitably be more computationally intensive. Workflow Auditors and referential views of data find conflicts between elements of information in use that should not be. Taken together, they allow information to be where it is supposed to be, when needed, and with as little ambiguity and uncertainty in its expression as theoretically possible. Such information, with this level of access and clarity, improves a workflow participant's ability to collaboratively reason and think abstractly. Thus, having a broader, richer and deeper outcome than what can be achieved today.
Workflow Auditor Point Tools
© 2008-2018 Yotta Data Sciences, Inc. All rights reserved.
* US Patents 9,122,825, 8,555,219, 8,266,571 and 7,685,545.
International Patents: China 200980129771.8, Japan 4768896, Korea 10-1580258
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